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硅通孔及硅转接板

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  • Si Interposer Frontend Process Capabilities 

    • 10 x 100um Void free filling

    • Min. 40um pitch of micro bump

    • 2-layer RDL routing layout

    • RDL Line/Space: min.10um/10um

  • Process Capabilities

    • TB/DB

    • Wafer thinning

    • Low cost via reveal

    • Double-sided RDL & bumping


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